1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to a low-noise silicon controlled rectifier.
2. Description of the Related Art
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event. Examples of known ESD protection schemes are shown in FIGS. 1 and 2. In deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a silicon controlled rectifier (SCR) has been used for ESD protection. An important feature of an SCR is its voltage-holding ability. An SCR can sustain high current and hold the voltage across the SCR at a low level, and may be implemented to bypass high current discharges associated with an ESD event.
FIG. 1 is a reproduction of FIG. 3 of U.S. Pat. No. 5,012,317 to Rountre, entitled xe2x80x9cElectrostatic Discharge Protection Circuit.xe2x80x9d Rountre describes a lateral SCR structure made up of a P+ type region 48, an N-type well 46, a P-type layer 44, and an N+ region 52. According to Rountre, a positive current associated with an ESD event flows through region 48 to avalanche a PN junction between well 46 and layer 44. The current then flows from layer 44 to region 52 across the PN junction and ultimately to ground, to protect an IC from the ESD event. However, an inherent disadvantage of the SCR structure shown in FIG. 1 is susceptibility to being accidentally triggered by a substrate noise, resulting in device latch-up.
FIG. 2 is a reproduction of FIG. 8B of U.S. Pat. No. 5,754,381 (the ""381 patent) to Ker, one of the inventors of the present invention. The ""381 patent is entitled xe2x80x9cOutput ESD Protection with High-Current-Triggered Lateral SCRxe2x80x9d and describes a modified PMOS-trigger lateral SCR (PTLSCR) structure and NMOS-trigger lateral SCR (NTLSCR) structure. The ""381 patent describes an NTLSCR 44 modified by an addition of a parasitic junction9-diode 66. The ""381 patent describes that the modified PTLSCR or NTLSCR structure prevents an SCR from being triggered by a substrate noise current, thereby preventing device latch-up.
Accordingly, the present invention is directed to a low-noise silicon controlled rectifier substantially and a substrate-biased low-noise silicon controlled rectifier that obviate one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a semiconductor substrate, a dielectric layer disposed over the semiconductor substrate, and a layer of silicon, formed over the dielectric layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion, the second p-type portion, the first n-type portion, and the second n-type portion overlap the isolation structure.
In one aspect of the invention, the first n-type portion is contiguous with the second p-type portion.
In another aspect of the invention, the layer of silicon further comprises a center portion disposed between the first n-type portion and the second p-type portion.
In yet another aspect of the invention, the layer of silicon further comprises a third n-type portion contiguous with the first p-type portion.
In still another aspect of the invention, the layer of silicon further comprises a fourth n-type portion contiguous with the first p-type portion and the first n-type portion, wherein the fourth n-type portion has a doped concentration lower than that of the third n-type portion.
Also in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, an isolation structure formed inside the semiconductor substrate, and a layer of silicon, formed over the isolation structure, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a center portion contiguous with the first n-type portion, a second p-type portion contiguous with the center portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion, the second p-type portion, the center portion, the first n-type portion, and the second n-type portion overlap the isolation structure.
In one aspect of the invention, the center portion of the layer of silicon is doped with an n-type impurity having a doped concentration lower than that of the first n-type portion.
In another aspect of the invention, the center portion of the layer of silicon is undoped.
Further in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure, formed inside the semiconductor substrate, contiguous with the well region, a second isolation structure, formed inside the semiconductor substrate, contiguous with a well region and spaced apart from the first isolation structure, a dielectric layer disposed over the well region and the first and second isolation structures, and a layer of silicon, formed over the dielectric layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion, and a second n-type portion contiguous with the second p-type portion, wherein at least a portion of the first p-type and first n-type portions overlap the first isolation structure and at least a portion of the second p-type and second n-type portions overlap the second isolation structure.
In one aspect of the invention, the well region is biased to control the layer of silicon for providing electrostatic discharge protection.
Additionally in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, an insulator layer disposed over the semiconductor substrate, a first silicon layer disposed over the insulator layer including a first isolation structure formed inside the first silicon layer, and a second isolation structure formed inside the first silicon layer and spaced apart from the first isolation structure. The integrated device also includes a dielectric layer disposed over the first silicon layer, and a second layer of silicon, disposed over the dielectric layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion, and a second n-type portion contiguous with the second p-type portion.
In one aspect of the invention, the portion of the first silicon layer between the first and second isolation structures is biased to provide electrostatic discharge protection.
Also in accordance with the present invention, there is provided a method for protecting a complementary metal-oxide semiconductor device from electrostatic discharge that includes providing a signal to the device through a complementary metal-oxide semiconductor circuit, providing a low-noise silicon controlled rectifier in the complementary metal-oxide semiconductor circuit, isolating the low-noise silicon controlled rectifier from a substrate of the complementary metal-oxide semiconductor circuit, and protecting the device from electrostatic discharge produced from the signal with the low-noise silicon controlled rectifier.
Further in accordance with the present invention, there is provided a method for protecting a silicon-on-insulator device from electrostatic discharge that includes providing a signal to the device through a silicon-on-insulator circuit, providing a low-noise silicon controlled rectifier in the silicon-on-insulator circuit, isolating the low-noise silicon controlled rectifier from a substrate of the silicon-on-insulator circuit, and protecting the device from electrostatic discharge with the low-noise silicon controlled rectifier.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.